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<title>CMSIS-Core (Cortex-M): ITM_Type Struct Reference</title>
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   <div id="projectname">CMSIS-Core (Cortex-M)
   &#160;<span id="projectnumber">Version 5.3.0</span>
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   <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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<p>Structure type to access the Instrumentation Trace Macrocell Register (ITM).  
</p>
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Data Fields</h2></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
<a class="anchor" id="a30bb2b166b1723867da4a708935677ba"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">__IM uint32_t ITM_Type::CID0</td>
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</div><div class="memdoc">
<p>Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 </p>

</div>
</div>
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<p>Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 </p>

</div>
</div>
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<p>Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 </p>

</div>
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<p>Offset: 0xFFC (R/ ) ITM Component Identification Register #3 </p>

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<p>Offset: 0xFBC (R/ ) ITM Device Architecture Register (Cortex-M33 only) </p>

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</div>
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<div class="memitem">
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          <td class="memname">__IOM uint32_t ITM_Type::IMCR</td>
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<p>Offset: 0xF00 (R/W) ITM Integration Mode Control Register </p>

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</div>
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<div class="memitem">
<div class="memproto">
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          <td class="memname">__IM uint32_t ITM_Type::IRR</td>
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</div><div class="memdoc">
<p>Offset: 0xEFC (R/ ) ITM Integration Read Register </p>

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</div>
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<p>Offset: 0xEF8 ( /W) ITM Integration Write Register </p>

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<p>Offset: 0xFB0 ( /W) ITM Lock Access Register </p>

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<div class="memitem">
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<p>Offset: 0xFB4 (R/ ) ITM Lock Status Register </p>

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<p>Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 </p>

</div>
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<p>Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 </p>

</div>
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<p>Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 </p>

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      <table class="memname">
        <tr>
          <td class="memname">__IM uint32_t ITM_Type::PID3</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 </p>

</div>
</div>
<a class="anchor" id="aad5e11dd4baf6d941bd6c7450f60a158"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IM uint32_t ITM_Type::PID4</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 </p>

</div>
</div>
<a class="anchor" id="af9085648bf18f69b5f9d1136d45e1d37"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IM uint32_t ITM_Type::PID5</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 </p>

</div>
</div>
<a class="anchor" id="ad34dbe6b1072c77d36281049c8b169f6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IM uint32_t ITM_Type::PID6</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 </p>

</div>
</div>
<a class="anchor" id="a2bcec6803f28f30d5baf5e20e3517d3d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IM uint32_t ITM_Type::PID7</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 </p>

</div>
</div>
<a class="anchor" id="af95bc1810f9ea802d628cb9dea81e02e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__OM { ... }    ITM_Type::PORT[32U]</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Offset: 0x000 ( /W) ITM Stimulus Port Registers </p>

</div>
</div>
<a class="anchor" id="a04b9fbc83759cb818dfa161d39628426"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IOM uint32_t ITM_Type::TCR</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Offset: 0xE80 (R/W) ITM Trace Control Register </p>

</div>
</div>
<a class="anchor" id="acd03c6858f7b678dab6a6121462e7807"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IOM uint32_t ITM_Type::TER</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Offset: 0xE00 (R/W) ITM Trace Enable Register </p>

</div>
</div>
<a class="anchor" id="ae907229ba50538bf370fbdfd54c099a2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IOM uint32_t ITM_Type::TPR</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Offset: 0xE40 (R/W) ITM Trace Privilege Register </p>

</div>
</div>
<a class="anchor" id="a962a970dfd286cad7f8a8577e87d4ad3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__OM uint16_t ITM_Type::u16</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Offset: 0x000 ( /W) ITM Stimulus Port 16-bit </p>

</div>
</div>
<a class="anchor" id="a5834885903a557674f078f3b71fa8bc8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__OM uint32_t ITM_Type::u32</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Offset: 0x000 ( /W) ITM Stimulus Port 32-bit </p>

</div>
</div>
<a class="anchor" id="ae773bf9f9dac64e6c28b14aa39f74275"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__OM uint8_t ITM_Type::u8</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Offset: 0x000 ( /W) ITM Stimulus Port 8-bit </p>

</div>
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